The present invention relates to a data processing apparatus for transmitting data among a plurality of electronic circuit units which are physically separated.
In a conventional data transmission system of an electronic computer or the like, the data system and the clock system are independent. Therefore, for instance, in the case where logic units which are connected to a data bus are used as packages, and transmission lines to connect the logic units are wired on a back board on which the packages are mounted, in the data transmission from the package serving as a source unit to the package serving as a sink unit, the clock system is devised to supply a clock signal of the same phase to both the source package and the sink package. However, in the data system, the phase of the sink package is delayed from that of the source package by the propagation delay time of the transmission line.
Such a conventional data transmission system will be described further in detail with reference to FIG. 5A.
In the diagram, reference numeral 1 denotes a 3-state output buffer gate. The 3-state output buffer gate is set into the enable state in the case where it is used as a source gate to transmit data to a bus, while it is set into the disable state in the case where it is not used as a source gate. The same shall apply hereinbelow in the specification. Reference numeral 2 indicates an input buffer gate; 3 an output flip-flop to determine the phase of, the data which is transmitted to the bus; 4 denotes an input flip-flop to receive data from the bus; 6 a data bus line; 7 a terminal resistor of the data bus line; 8a to 8z packages in which electronic parts such as LSI components and the like are installed; and T.sub.A and T.sub.B clock signal which are common among the packages. The clock signal T.sub.A and T.sub.B are outputs from a clock phase adjuster 10 provided in each package. Each of the clock phase adjusters 10 receives clock signal from a clock generator 9 provided in only the package 8a and adjusts the clock signal T.sub.A and T.sub.B to substantially the same phase in each package. The clock signal T.sub.A and T.sub.B are used as set timing signals of the output flip-flop 3 and the input flip-flop 4, respectively.
A construction of the data bus has been disclosed in "VLSI computer I", Chapter 4, Item 4 and 5 (Input/Output Control), Iwanami Koza Microelectronics, No. 8, pages 263 to 274, Dec. 10, 1984.
A time chart for the system of FIG. 5A is shown in FIG. 5B. In FIGS. 5B, (1) to (4) indicate data waveforms on the side of the packages 8a, 8b, 8c, and 8z in the case of transmission data from the package 8a to the packages 8b, 8c, and 8z, respectively.
In the conventional data transmission system as shown in FIG. 5A, in-all of the packages, the phase difference between the clocks T.sub.A and T.sub.B is minimized. However, as shown in FIG. 5B, for instance, the data transmission time in the case of transmitting from the package 8a to the package 8b differs from the data transmission time in the case of transmitting from the package 8a to the package 8z. Thus, there is a problem such that in the case of transmitting high-speed data of a short data period, the propagation delay time of the transmission line cannot be ignored, and it is impossible to assure a set-up time and a holding time of the flip-flop to fetch the data by the sink package, and the data cannot be correctly transmitted.